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AOM / Мельник А

10.7. Література до розділу 10

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  2. Bhandarkar, D. P. [1995], Alpha Architecture Implementations, Digital Press, Newton, Mass.

  3. BORG, A., R. E. KESSLER, AND D. W. WALL [1990]. "Generation and analysis of very long add­ress traces", Proc. 17th Annual Int'l Symposium on Computer Architecture (Cat. No. 90CH2887-8), Seattle, May 28-31, IEEE Computer Society Press, Los Alamitos, Calif., 270-9.

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  5. Clark, D. W. [1983]. "Cache performance of the VAX-W780", ACM Trans, on Computer Systems 1:1,24-37.

  6. Conti, C, D. H. GIBSON, AND S. H. P1TKOWSKY [1968J. "Structural aspects of the Sys­tem/360 Model 85, Part I: General organization", IBM Systems J. 7:1, 2-14.

  7. CRAWFORD, J. H. AND P. P. GELSINGER [1987]. Programming the 80386, Sybex, Alameda, Calif:

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  2. FARKAS, K. I. AND N. P. JOUPP1 [1994]. "Complexity/performance tradeoffs with non-bloc­king loads'; Proc. 21st Annual Int'l Symposium on Computer Architecture, Chicago (April).

  3. Gao, Q. S. [1993]. "The Chinese remainder theorem and the prime memory system", 20th Annual Int'l Symposium on Computer Architecture ISCA '20, San Diego, May 16-19, 1993. Computer Architect­ure News 21;:2 (May), 337—40.

  4. Gee, J. D., M. D. Hill, D. N Pnevmatikatos, and A. J. Smith [1993]. "Cache performance of the SPEC92 benchmark suite", IEEE Micro 13:4 (August), 17-27.

  5. HILL, M. D [1987]. Aspects of Cache Memory and Instruction Buffer Performance, Ph.D. Thesis, University of Calif, at Berkeley, Computer Science Division, Tech. Rep. UCB/CSD 87/381 (November).

  6. Hill, M. D. [1988]. "A case for direct mapped caches", Computer 21:12 (December), 25-40.

  7. JOUPPI, N. P. [1990]. "Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers", Proc. 17th Annual Int'l Symposium on Computer Architecture (Cat. No. 90CH2887-8), Seattle, May 28-31, 1990. IEEE Computer Society Press, Los Alamitos, Calif, 364-73.

  8. Kilburn, T, D. B. G. Edwards, M. J. Lanigan, and E H. Sumner [1962], "One-level storage system", IRE Trans, on Electronic Computers EC-11 (April) 223-235. Also appears in D. P. Siewiorek, C. G. Bell, and A. Newell, Computer Structures: Principles and Examples (1982), McGraw-Hill, New York, 135-148.

  9. Kroft, D. [1981]. "Lockup-free instruction fetch/prefetch cache organization", Proc. Eighth Ann­ual Symposium on Computer Architecture (May 12-14), Minneapolis, 81-87.

  10. Lam, M. S., E. Е. Rothberg, and M. E. Wolf [1991]. "The cache performance and optimizatio­ns of blocked algorithms", Fourth Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, Santa Clara, Calif, April 8-11. SIGPLAN Notices 26:4 (April), 63-74.

  11. Lebeck, A. R. and D. A. WOOD [1994]. "Cache profiling and the SPEC benchmarks: A case study" Computer 27-Л0 (October), 15-26.

  12. Liptay, J. S. [1968]. "Structural aspects of the System/360 Model 85, Part II: The cache", IBM Systems J. 7:1, 15-21.

  13. McFarling, S. [1989]. "Program optimization for instruction caches", Proc. Third Int'l Conf. on Architectural Support for Programming Languages and Operating Systems (April 3-6), Boston, 183-191.

  14. Mowry, T. C, S. Lam, and A. Gupta [1992]. "Design and evaluation of a compiler algorithm for prefetching", Fifth Int'l Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS-V), Boston, October 12-15 , SIGPLAN Notices 27:9 (September), 62-73.

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  2. PRZYBYLSKI, S. A. [1990]. Cache Design: A Performance-Directed Approach, Morgan Kauf-mann Publishers, San Mateo, Calif.

  3. PRZYBYLSKI, S. A., M. Horowitz, AND J. L. Hennessy [1988], "Performance tradeoffs in cache design", Proc. 15th Annual Symposium on Computer Architecture (May-June), Honolulu, 290-298.

  4. Saavedra-Barrera, R. H. [1992]. CPU Performance Evaluation and Execution Time Prediction Using Narrow Spectrum Benchmarking, Ph.D. Dissertation, University of Calif., Berkeley (May).

  5. Samples, A. D. AND P. N. Hilfinger [1988]. "Code reorganization for instruction caches", Tech. Rep. UCB/CSD 88/447 (October), University of Calif., Berkeley.

  6. Sites, R. L. (ED.) [1992]. Alpha Architecture Reference Manual, Digital Press, Burlington, Mass.

  7. Smith, A. J. [1982]. "Cache memories", Computing Surveys 14:3 (September), 473-530.

  8. Smith, J. E. and J. R. Goodman [1983]. "A study of instruction cache organizations and replace­ment policies", Proc. 10th Annual Symposium on Computer Architecture (June 5-7), Stockholm, 132-137.

  9. STRECKER, W. D. [1976]. "Cache memories for the PDP-11?," Proc. Third Annual Symposium on Computer Architecture (January), Pittsburgh, 155-158.

  10. Torrellas, J., A. Gupta, and J. Hennessy [1992], "Characterizing the caching and synchro­nization performance of a multiprocessor operating system", Fifth Int'l Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS-V), Boston, October 12-15, SIGPLAN Notices27:9 (September), 162-74.

  11. Wang, W.-H., J.-L. Baer, and H. M. Levy [1989]. "Organization and performance of a two-level virtual-real cache hierarchy", Proc. 16th Annual Symposium on Computer Architecture (May 28-June 1), Jerusalem, 140-148.

  12. Wilkes, M. [1965]. "Slave memories and dynamic storage allocation", IEEE Trans. Electronic Computers EC-14:2 (April), 270-271.

  13. Wilkes, M. V. [1982]. "Hardware support for memory protection: Capability implementati­ons", Proc. Symposium on Architectural Support for Programming Languages and Operating Sys­tems (March 1-3), Palo Alto, Calif., 107-116.

  14. Wulf, W. A., R. Levin, and S. P. HARBISON [1981], Hydra/C.mmp: An Experimental Compu­ter System, McGraw-Hill, New York.